Mustafa Munawar Shihab

I am a Ph.D. candidate in the Department of Electrical and Computer Engineering at the University of Texas at Dallas. Under the supervision of Dr. Yiorgos Makris, my research pivots around Computer Architecture, Reconfigurable Computing and their implications in Hardware Security. Specifically, my dissertation builds on: (i) developing a novel CAD flow and testing mechanism for the Transistor-level Programmable Fabric (TRAP), and (ii) applying the fabric to address various open problems in hardware Security, such as, design obfuscation, hardware Trojan detection, etc.

Prior to this, I received my MS in Electrical Engineering from Auburn University (Alabama, USA), where I worked on low-power VLSI design and testing. I received my BS in Electronic and Telecommunication Engineering from the North South University (Dhaka, Bangladesh). I also worked as a Software Architect Intern in the SSG group at Intel. For the long haul, I look forward to a career where my circuit-to-system, cross-platform experience can be applied and appreciated.

Research Interests

Computer Architecture || Hardware Security || Reconfigurable Computing || Memory Technology (DRAM, MRAM, NAND Flash)

Technical Skill Set

Programming Languages: Python, Verilog, C, C++, VHDL
Hardware Design & Simulation: LTspice, Mentor ModelSim/Questa, MATLAB
CAD Implementation: Synopsys DC, Xilinx Vivado, Intel Quartus, Mentor Precision RTL, TimberWolf, VPR
Operating Systems: Microsoft Windows, Linux, Mac OS

Education

PhD in Electrical Engineering

The University of Texas at Dallas - Richardson, Texas

Fall 2014 - Current

CGPA: 4.00/4.00

Dissertation: Enabling Hardware Security and In-Field Hardware Update Through a Novel Hybrid IC Design Methodology

MS in Electrical Engineering

Auburn University - Auburn, Alabama

2011 - 2013

CGPA: 3.88/4.00

Thesis: A High-Voltage On-Chip Power Distribution Network

BS in Electronic and Telecommunication Engineering

North South University - Dhaka, Bangladesh

2004 - 2008

CGPA: 3.80/4.00

Thesis: A Comparative Study of the New 5T and the Standard 6T SRAM Designs - A possible solution towards High-Density SRAMs

Publications

Peer-Reviewed Journals

[1] CAPE: A Cross-layer Framework for Accurate Microprocessor Power Estimation

Monir Zaman, Mustafa M. Shihab, Ayse K. Coskun, and Yiorgos Makris

Integration - The VLSI Journal, 2019

[2] ReveNAND: A Fast-Drift-Aware Resilient 3D NAND Flash Design

Mustafa M. Shihab, Jie Zhang, Myoungsoo Jung, and Mahmut Kandemir

ACM Transactions on Architecture and Code Optimization (TACO) - Volume 15, Issue 2, Article No. 17, 2018

Conference & Workshop Papers

[16] CASPER: CAD Framework for a Novel Transistor-Level Programmable Fabric

Mustafa M. Shihab, Bharath Ramanidharan, Gaurav Rajavendra Reddy, Jingxian Tian, William Swartz Jr., Benjamin Carrion Schaefer, Carl Sechen, and Yiorgos Makris

IEEE ISCAS 2020 (Accepted)

[15] ATTEST: Application-Agnostic Testing of a Novel Transistor-Level Programmable Fabric

Mustafa M. Shihab, Bharath Ramanidharan, Suraag Sunil Tellakula, Gaurav Rajavendra Reddy, Jingxian Tian, Carl Sechen, and Yiorgos Makris

IEEE VTS 2020

[14] An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs

Bo Hu, Mustafa M. Shihab, Yiorgos Makris, Benjamin Carrion Schaefer and Carl Sechen

IEEE/ACM DATE 2020

[13] Extending the Lifetime of Coarse-grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage

Bo Hu, Mustafa M. Shihab, Yiorgos Makris, Benjamin Carrion Schaefer and Carl Sechen

IEEE FPT 2019

[12] Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA

Bo Hu, Jingxiang Tian, Mustafa M. Shihab, Gaurav Rajavendra Reddy, William Swartz, Yiorgos Makris, Benjamin Carrion Schaefer and Carl Sechen

ACM GLSVLSI 2019

[11] Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming

Mustafa M. Shihab, Jingxiang Tian, Gaurav Rajavendra Reddy, Bo Hu, William Swartz Jr., Benjamin Carrion Schaefer,
Carl Sechen and Yiorgos Makris

IEEE/ACM DATE 2019

[10] Addressing Fast-Detrapping for Reliable 3D NAND Flash Design

Mustafa M. Shihab, Jie Zhang, Myoungsoo Jung, and Mahmut Kandemir

Non-Volatile Memories Workshop (NVMW) 2019 [Memorable Paper Award Finalist]

[9] Energy Efficient Power Distribution on Many-Core SoC

Mustafa M. Shihab and Vishwani Agrawal

IEEE VLSID 2019

[8] Towards a Cross-Layer Framework for Accurate Power Modeling of Microprocessor Designs

Monir Zaman, Mustafa M. Shihab, Ayse K. Coskun, and Yiorgos Makris

IEEE PATMOS 2019

[7] Couture: Tailoring STT-MRAM for Persistent Main Memory

Mustafa M. Shihab, Jie Zhang, Joseph Callenes-Sloan, and Myoungsoo Jung

USENIX INFLOW 2016

[6] SpinDIMM: A Reliable Memory Design with Tailored STT-MRAM and Reinforcement Learning

Mustafa M. Shihab, Myoungsoo Jung, and Joseph Callenes-Sloan

IEEE SELSE 2016

[5] OpenNVM: An Open-Sourced FPGA-based NVM Controller for Low Level Memory Characterization

Jie Zhang, Gieseo Park, Mustafa M. Shihab, David Donofrio, John Shalf and Myoungsoo Jung

IEEE ICCD 2015

[4] NVM-Charade: An Open-Sourced FPGA Based NVM Characterization Scheme

Gieseo Park, Mustafa M. Shihab, Lubaba Nahar, Wonil Choi, David Donofrio, John Shalf, Myoungsoo Jung

IEEE/ACM WARP (ISCA) 2015

[3] GPUdrive: Reconsidering Storage Accesses for GPU Acceleration

Mustafa M. Shihab, Karl Taht, and Myoungsoo Jung

IEEE/ACM ABSD (ISCA) 2014

[2] Exploring Area, Power and Latency Dynamics of STT-MRAM to Substitute for Main Memory

Youngbin Jin, Mustafa M. Shihab, and Myoungsoo Jung

IEEE/ACM Memory Forum (ISCA) 2014

[1] Power, Energy and Thermal Considerations in SSD-Based I/O Acceleration

Jie Zhang, Mustafa M. Shihab, and Myoungsoo Jung

USENIX HotStorage 2014

Google Scholar Profile

Experience

Graduate Research Assistant

Department of ECE, UT Dallas - Richardson, Texas

May 2015 - June 2016, May 2017 - Current

Responsibilities: Perform individual and collaborative research on hardware security, reconfigurable computing, emerging memory technologies (e.g., STT-MRAM and 3D NAND Flash), and develop required architectural support for their reliable implementation.

Software Architect Intern

Software Services Group, Intel Corporation - Santa Clara, Californica

June 2016 - Dec 2016

Responsibilities: Leveraged microarchitecture dependent and independent metrics to predict system performance for applications from client, cloud, and HPC domains. Extended the current profiling methodology for specific set of workloads running on Mac OS.

Graduate Teaching Assistant

Department of ECE, UT Dallas - Richardson, Texas

August 2014 - May 2015, Jan 2017 - May 2017

Courses: Computer Architecture, Microprocessor Systems.

Graduate Research Assistant

Department of ECE, Auburn University - Auburn, Alabama

August 2012 - July 2013

Responsibilities: Explored open problems in low-power VLSI design and testing that culminated in the MS thesis.

Graduate Research Assistant

Alabama Microelectronics Science and Technology Center (AMSTC), Auburn University - Auburn, Alabama

May 2011 - July 2013

Responsibilities: Assisted in managing the 4000 sq.ft. Class-100 clean-Room equipped with a range of state-of-the-art equipment.